1. Field of the Invention
The invention relates generally to a semiconductor memory device. More particularly, the invention relates to a non-volatile memory device and a method of programming the same.
A claim of priority is made to Korean Patent Application No. 2004-89955 filed on Nov. 5, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Semiconductor memories are used in a wide array of electronic applications ranging from personal computers to embedded devices, and from industrial technologies to consumer electronics, as examples. In many cases, the speed and/or capacity of the semiconductor memories pose a performance bottleneck for the devices that use them, and accordingly, there is a constant demand to improve the performance of semiconductor memories by increasing their speed and degree of integration. In order to improve the performance of semiconductor memories, new manufacturing techniques are needed, including processing techniques capable of creating faster, more highly integrated semiconductor memories.
Semiconductor memory devices are generally grouped into two broad categories including volatile semiconductor memory devices and non-volatile semiconductor memory devices. Briefly, volatile semiconductor memory devices provide persistent data storage as long as power is supplied to the devices, but they lose the data once the power is cut off. Non-volatile semiconductor memory devices, on the other hand, provide persistent data storage even when power to the devices is cut off or suspended.
Because of their ability to provide persistent data storage even when power is cut off, non-volatile memory devices are commonly used to provide long term storage for data such as program files and microcode. Non-volatile memory devices are frequently used in application areas such as personal computers, aerospace electronic engineering, communication systems, and consumer electronics.
One special class of non-volatile memory is non-volatile random access memory (nvRAM). A nvRAM may be employed in a system requiring certain benefits of both volatile and non-volatile memories. For example, one type of nvRAM is formed by connecting a static random access memory (SRAM) to a battery so as to prevent the nvRAM from losing its data when system power is cut off. Accordingly, the nvRAM provides fast read/write times while still retaining its data when system power is cut off.
Some non-volatile semiconductor memories are adapted for reprogramming and others are not. For example, due to design limitations, a mask-programmed read-only memory (MROM) or a programmable read-only memory (PROM) can be programmed only once during its lifetime. Erasable programmable read-only memory (EPROM) can be reprogrammed, but only after exposing it to ultraviolet light for several minutes to erase previously stored data. Electrically erasable programmable read-only memory (EEPROM), on the other hand, provides efficient reprogramming capability by allowing memory cells to be reprogrammed by simply applying electric fields to the cells. An EEPROM can generally be reprogrammed more than one hundred thousand times during its lifetime.
Flash memory is a special type of EEPROM in which multiple memory blocks are erased or programmed by a single programming operation. The performance of flash memory is generally superior to that of normal EEPROM, which only allows one memory block to be erased or programmed at a time. In addition, flash memory provides fast access times for read operations and is resistant to physical shock, thus making it an attractive option for high performance portable devices such as cellular phones and personal digital assistants (PDAs).
A typical flash memory comprises an array of transistors called cells, wherein each cell has a source and a drain formed on a substrate and two gate structures formed on the substrate between the source and the drain terminals. The two gate structures generally comprise a floating gate (FG) surrounded by an insulating layer and a control gate (CG) formed on the floating gate. The floating gate is used to store electrons determining a logic state for the cell.
A flash memory cell is read by placing a voltage on its control gate and detecting whether a current flows between its drain and source. Depending on how many electrons are stored in the floating gate, the voltage applied to the control gate will either allow current to flow between the drain and the source or it will not. For example, where a large number of electrons is stored in the floating gate, the electrons have a canceling effect on the voltage applied to the control gate, thereby affecting whether current flows between the drain and the source. In other words, the electrons stored in the floating gate modify the threshold voltage of the cell, i.e. the voltage that has to be applied to the control gate in order for current to flow between the drain and the source.
Although a typical flash memory cell stores only 1-bit of information, a flash memory cell may be designed to store more than one bit by varying the amount of charge accumulated in its floating gate. In a so-called “multi-level” flash memory cell, the logic state of the cell is determined by measuring the amount of current that flows between the drain and the source when a voltage is applied to the control gate.
Due to variations in flash memory cells such as their geometry or a voltage used to program the memory cells, there tends to be variation in the threshold voltages of flash memory cells that have been programmed. Where the variation in the threshold voltages is not properly regulated, it can cause the flash memory to have poor performance.
In order to regulate a threshold voltage distribution for programmed memory cells, the memory cells are generally programmed using an incremental step pulse programming (ISPP) scheme such as that illustrated by FIG. 1. Referring to FIG. 1, a program voltage VWL is applied to a wordline. Program voltage VWL is increased in multiple program loop iterations executed during a programming operation. Each program loop comprises a programming period and a program verification period. In each program loop, programming voltage VWL is incremented by an amount ΔV. During the programming operation, a threshold voltage Vt of a cell being programmed increases by amount ΔV in each program loop. In order to minimize variation in the threshold voltage distribution, amount ΔV should be small. As the increment ΔV becomes smaller, the number of program loops becomes larger. Since there is a tradeoff between the number of program loops required and the variance of the threshold voltage distribution, ΔV should be chosen to minimize the variance of the threshold voltage as much as possible without significantly limiting the performance of the memory device by requiring too many program loops.
A programming scheme for a non-volatile memory device using ISPP is disclosed, for example, in U.S. Pat. No. 6,266,270. Circuits for generating programming voltages using ISPP are disclosed, for example, in U.S. Pat. No. 5,642,309 and in Korean Patent Publication No. 2002-39744.
When programming a NOR flash memory device using an ISPP scheme as described above, a wordline voltage of about 10V is applied to a control gate of a flash cell, a bitline voltage of about 5V-6V is applied to the drain of the flash cell and a bulk voltage lower than 0 (e.g., −1V) is applied to a bulk or substrate of the flash cell. In general, a cell current Icell flowing through a memory cell is proportional to (VGS−Vt)2, where Vt is a threshold voltage of the memory cell and VGS is a gate to source voltage of the memory cell. The bitline voltage is generated and maintained by a first charge pump (not shown) and the bulk voltage is generated and maintained by a second charge pump (also not shown). Where the amount of current flowing on the bulk line exceeds the capacity of the second charge pump, the bulk voltage rises above a predetermined voltage level. When the bulk voltage rises above a predetermined voltage level, the threshold voltage of the flash memory cell may fail to increase by a desired amount during a programming loop, as indicated by a broken line in FIG. 1. Accordingly, as more programming loops are executed, the difference between the wordline voltage and the threshold voltage may become larger and larger. As a result, the quality of programming may degrade to a point of program failure.
In order to prevent programming failures from occurring due to an elevated bulk voltage, new techniques are needed for programming flash memory cells.